Chapter 3: UW-MEMS Layout Example

Layout Generation

This chapter presents a basic example of MEMS relay to illustrate the UW-MEMS layout generation step-by-step for designers. 聽Experienced designers typically use tools such as L-EDIT and Cadence to generate the layouts for the various layers.聽 However, any tool that can generate layouts in GDSII formats can be used to submit designs to UW-MEMS. This example is given to provide beginners in the field with layout illustrations to help them understand the guidelines given in chapter 2.

Consider the MEMS relay shown in Figure 3.1. The relay consists of a cantilever beam anchored to an input signal line.聽 The cantilever can be pulled down using electrostatic actuation so that its tip makes contact with the output signal line and hence closes the relay. The actuation is performed using a pad covered by SiO2 (i.e. dielectric). The two DC bias pads are connected to the actuation pad and the input signal line using high resistivity TiW traces. A dimple is added to the cantilever tip to ensure contact with the output signal line. Below is a description of the seven masks used for production of a MEMS relay based on the nine layout layers detailed in chapters 1 and 2.

  • Fig. 3.2a shows the layout of Mask #1 (produced from 鈥TiW鈥 layer).聽 This mask shows the two high resistivity traces that connect the DC bias pads to the actuation pad and the input signal line.聽 The mask is 鈥Light Field鈥. Note that the TiW traces must be made at least 20 碌m longer on each side in order to overlap the gold (see Design Rules: Overlaps & Enclosures).
  • Fig. 3.2b shows the layout of Mask #2 (produced from 鈥D1鈥 and 鈥D1HOLE鈥 layers). This mask shows the insulation layer that covers the bias lines. The mask is 鈥Light Field鈥.
  • Fig. 3.2c shows the layout of Mask #3 (produced from 鈥G1鈥 layer). This mask shows the input/output signal lines, actuation electrode and the two bias pads.聽 The mask is 鈥Light Field鈥.
  • Fig. 3.2d shows the layout of Mask #4 (produced from 鈥D2鈥 layer). This mask shows the insulation layer that covers the actuation electrode. The mask is 鈥Light Field鈥.
  • Fig. 3.2e shows the layout of Mask #5 (produced from 鈥A鈥 layer). This mask defines the anchor location for connection of G2 and G1 metals. The mask is 鈥Dark Field鈥.
  • Fig. 3.2f shows the layout of Mask #6 (produced from 鈥D鈥 layer). This mask defines the dimple location which is connected to the tip of the cantilever. The mask is 鈥Dark Field鈥.
  • Fig. 3.2g shows the layout of Layer #8 (鈥G2鈥). This layer shows the cantilever. The layer is 鈥Light Field鈥. Besides, Fig. 3.2h shows the layout of Layer #9 (鈥G2R鈥) that is 鈥Dark Field鈥. This layer will be subtracted from 鈥G2鈥 layer mask by CIRFE personnel to generate the Mask #7.

Note:
The cantilever length needs to be extended at the anchor location in order to make sure that 鈥G1鈥 and 鈥G2鈥 enclose 鈥A鈥 (see Design Rules: Overlaps & Enclosures).

Figure 3.1: A MEMS Relay

Figure 3.1: A MEMS Relay

听听

Figure 3.2a: Mask #1 (鈥淭颈奥鈥)
Figure 3.2a: Mask #1 (鈥淭颈奥鈥)

Figure 3.2b: Mask #2 (鈥淒1鈥-
Figure 3.2b: Mask #2 (鈥凄1鈥-"顿1贬翱尝贰")

Figure 3.2c: Mask #3 (鈥淕1鈥)
Figure 3.2c: Mask #3 (鈥淕1鈥)

Figure 3.2d: Mask #4 (鈥凄2鈥)
Figure 3.2d: Mask #4 (鈥凄2鈥)

Figure 3.2e: Mask #5 (鈥淎鈥)
Figure 3.2e: Mask #5 (鈥淎鈥)

Figure 3.2f: Mask #6 (鈥淒鈥)
Figure 3.2f: Mask #6 (鈥淒鈥)

Figure 3.2g: Layer 鈥滸2鈥
Figure 3.2g: Layer 鈥滸2鈥

Figure 3.2h: Layer 鈥滸2R鈥
Figure 3.2h: Layer 鈥滸2R鈥

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