Introduction
These design guidelines and rules were determined during the process development stage and several microfabrication runs carried out at CIRFE cleanroom facility. The rules identify the physical and geometrical limitations of individual process steps. The herein presented guidelines are extremely important and must be considered at the design stage. If the guidelines are not followed closely by UW-MEMS users, the fabricated devices will not meet the specifications and will probably fail or malfunction.
In general, there are two types of rules. The first type of rules specifies the minimum feature sizes and minimum feature separation distances within a single layout layer, i.e. intra-layer design rules. The minimum feature size refers to the minimum side length of a trace that is feasible using UW-MEMS. In other words, if this rule is violated there is no guarantee that the feature will be produced on the wafer. Similarly, the minimum separation distance between adjacent features must comply with the design rules in order to be feasible. Failure to follow the minimum spacing design rule results in a merged feature.
The second type of design rules specifies the inter-level crossovers (overlaps) and separation distances. This is mainly imposed by the inevitable relative misalignment of the different layout layers throughout fabrication, and it will be shortly detailed. Both types of design rules are considered mandatory and should be followed closely by the designer.
Design Rules: General Outlines
The layout design rules for the UW-MEMS process are explained in the following tables and illustrated in schematic format following the tables. First, Table 1 outlines the different layer names, corresponding material thicknesses as well as layer numbers and description.
Table 1: Layer Names, Material Thicknesses, Layers Order, Layer Description and Comments
Layer Name | Material Thickness | Layer Order | Layer Description | Comments |
---|---|---|---|---|
鈥淭颈奥鈥 | 50nm | 1 | Resistive Voltage Biasing听 | Resistive Layer |
鈥凄1鈥 & 鈥凄1贬翱尝贰鈥 | 0.7碌尘 | 2 & 3 | Dielectric | 0.7碌尘 SiO2 to cover the bias lines |
鈥淕1鈥 | 1碌尘 | 4 | Conductive Layer | 40nm evaporated Cr + 70nm evaporated Au + 0.9碌m electroplated Au |
鈥凄2鈥 | 0.7碌尘 | 5 | Dielectric | 50nm TiW + 0.7碌尘 SiO2 |
鈥淎鈥 & 鈥凄鈥 | 2.5碌尘 | 6 & 7 | Sacrificial Layer | 2.5碌尘 Anchor and 1碌尘 Dimple openings |
鈥淕2鈥 & 鈥淕2搁鈥 | 2碌尘 | 8 & 9 | Conductive Layer | 70nm sputtered Au + 1.9碌m electroplated Au |
Table 2 outlines the layers that are used during the microfabrication process.听 Please note that for the case of 鈥淟ight Filed鈥, you draw the features that you want to be remained on the wafer.听 For example, for TiW layer patterning, you draw the features or traces such as bias lines. For the 鈥淒ark Field鈥, you draw the parts you want to be removed from the corresponding layer such as release holes or openings for anchors and dimples.听 Please pay special attention to this concept. Failure to do so will result in a reverse polarity devices.
In other words, for D1HOLE and G2R, you draw only the location of dielectric openings and release holes in gold, respectively. These layers will be subtracted from the D1 and G2 layers by CIRFE personnel prior to printing the second and seventh lithographic masks.
Table 2: Layer Names, Layer Polarity Type and Comments
Layer Names | Polarity | Comments |
---|---|---|
鈥淭颈奥鈥 | Light Field | Patterning TiW |
鈥凄1鈥 | Light Field | Patterning D1 without openings |
鈥凄1贬翱尝贰鈥 | Dark Field | Additional layer for openings on the D1 layer |
鈥淕1鈥 | Light Field | Patterning G1 |
鈥凄2鈥 | Light Field | Patterning D2 |
鈥淎鈥 | Dark Field | Opening anchors between G1 and G2 |
鈥凄鈥 | Dark Field | Dimples of G2 for contacts of the switches as well as preventing the stiction of large plates |
鈥淕2鈥 | Light Field | Patterning G2 |
鈥淕2搁鈥 | Dark Field | Additional layer for release holes of the G2 layer. |
Table 3 presents the lithographic mask numbers with the respective GDSII indices of their constituting layout layers. GDSII is the only format that UW-MEMS accept from all users.听 Please use the GDSII numbers that are specified in the table for each layout layer to avoid confusion. Layers D1HOLE and G2R are just employed to create the openings in the D1 layer and the release holes in G2 layer, respectively. No lithographic masks are printed specifically for these layers. Please note that the dimples are meant for small features.听 Nominal surface area is 10碌m by 10碌m. However, they can be used for long lines, but it is recommended that the width of the lines be 10碌m.
Table 3: UW-MEMS Masks and GDSII Layer Indices
Lithographic Mask | Layer Name(s) | GDSII Index |
---|---|---|
Mask #1 | TiW | 101 |
Mask #2 | D1听鈥撎D1HOLE | 102 - 110 |
Mask #3 | G1 | 103 |
Mask #4 | D2 | 104 |
Mask #5 | A | 105 |
Mask #6 | D | 106 |
Mask #7 | G2听鈥撎G2R | 107 - 109 |
Design
Rules:
Overlaps
&
Enclosures
Generally, the following guidelines should be considered:
- For overlaps and enclosures of the layers, up to 10mm of misalignment between the layers is assumed. This is due to the limitations of our photolithography system. This is an advisory design rule.
- TiW lines are designated for the DC bias lines with no current flow.听 This layer is very thin, and it is not intended for power transfer.
The following outlines the specific layout design rules to which close attention must be paid. It is worth emphasizing that the minimum feature size and minimum spacing between features are limits to which the designers should strictly adhere. Ideally, adding a 10mm additional safety margin to these numbers may increase the yield of fabrication. Users can have round, orthogonal or any arbitrary shape in your layout. The release holes must be 10mm x 10mm squares with edge to edge distances not exceeding 20碌m. Please do not use this layer to define geometries. The features are embedded to provide access to underneath the structural layer during the release purposes.
1.听听听 鈥淭颈奥鈥 resistive DC bias lines:

Description |
Rule
Label
|
Value
(碌m)
|
---|---|---|
Width/Length of听TiW | TiW1 | 鈮听10 |
Spacing of听TiW | TiW2 | 鈮听10 |
2.听听听 First Dielectric 鈥凄1鈥 stacked with 鈥淭颈奥鈥 and Gold 鈥淕1鈥:

Description |
Rule
Label
|
Value
(碌m)
|
---|---|---|
Extension of听TiW听from听D1 | TiW3 | 鈮听20 |
Width/Length of听D1 | D11 | 鈮听15 |
Spacing of听D1 | D12 | 鈮听15 |
Overlap of听D1听with听TiW | D13 | 鈮听5 |
Extension of听D1HOLE听from听TiW | D14 | 鈮听10 |
Width/Length of听D1HOLE | D15 | 鈮听35 |
Overlap of听G1听pad with听TiW听or听D1 | G13 | 鈮听15 |
Overlap of听G1听pad with听TiW | G14 | 鈮听10 |
听听Note: TiW lines MUST be always covered with D1, G1, or both.
3.听听听 First Gold 鈥淕1鈥:

Description | Rule Label | Value (碌m) |
---|---|---|
Width/Length of听G1 | G11 | 鈮听10 |
Spacing of听G1 | G12 | 鈮听10 |
4. Second Dielectric 鈥凄2鈥 on top of TiW adhesion layer:

Description | Rule Label | Value (碌m) |
---|---|---|
Width/Length of听D2 | D21 | 鈮听15 |
Spacing of听D2 | D22 | 鈮听15 |
Overlap of听D2听with听G1 | D23 | 鈮听10 |
Overlap of听D2听with听A | D24 | 鈮听15 |
Spacing of听D2听from听G1 | D25 | 鈮听15 |
Feature size of听A听over听D2 | AD | 鈮听200 |
Note: D2 over 2 separated trances MUST be separated.
Note: Anchor on top of D2 cannot be used as mechanical support but can be used for Metal-Insulator-Metal (MIM) capacitor.
5. Anchor 鈥淎鈥 Openings:

Description | Rule Label | Value (碌m) |
---|---|---|
Width/Length of听A | A1 | 鈮 10 |
Spacing of听A | A2 | 鈮听10 |
Overlap of听G1听with听A (A听MUST be covered with听G1) | A3 | 鈮10 |
Overlap of听G2听with听A (A听MUST be covered with听G2) | A4 | 鈮听5 |
Spacing of听D2听from听A | A5 | 鈮听10 |
6.
Dimple
鈥凄鈥
Openings:

Description | Rule Label | Value (碌m) |
---|---|---|
Width/Length of听D | DIM1 | 鈮听10 |
Spacing of听D | DIM2 | 鈮听10 |
Overlap of听G2听with听D | DIM3 | 鈮听5 |
Overlap of听G1听with听D | DIM4 | 鈮听5 |
7. Second Gold 鈥淕2鈥:

Description | Rule Label | Value (碌m) |
---|---|---|
Width/Length of听G2 | G21 | 鈮听10 |
Spacing of听G2 | G22 | 鈮听10 |
Ratio of听G23/G21听when听G2听is not anchored to听G1 | G23/G21 | 鈮听30 |
Non-anchored length of听G2 | G23 | 鈮听1200 |
Width/Length of听G2R | G24 | 鈮听10 |
Spacing of听G2R听(edge-to-edge) | G25 | 鈮听20 |
Spacing of听G2R听from听G2听edge | G26 | 鈮听10 |
Spacing of听G2R听from听A | G27 | 鈮听10 &听听鈮听30 |

Note: This configuration results in short-circuit between the two G1 traces due to the conductive TiW thin layer underneath the D2 layer.
9. Caution 2:

Note: This configuration may result in short-circuit between the G1 and G2 traces through D2 layer.
Material Properties
Table 4 reports some of the mechanical and electrical properties of the UW-MEMS process. The data is based on the measurements performed on earlier UW-MEMS processes and agree well with the nominal known values in the literature. Designers can use the existing values in the literature for the other material properties.
Table 4: Physical properties of UW-MEMS materials
Material |
Residual
Stress (MPa) |
Conductivity (鈩-1/m) |
Sheet
Resistance (鈩/鈻) | Relative Permittivity |
---|---|---|---|---|
TiW of Resistive Bias Lines | ------ | ------ | 20* | ------ |
SiO2 of D1 and D2 | ------ | ------ | ------ | 4 |
Au of G1 and G2 |
190 +/- 30% 听Tensile | 3.6褏107 | ------ | ------ |
*Higher resistivity (500惟/鈻) will be optionally available.